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<div class="header">
  <div class="summary">
<a href="#groups">API Reference</a>  </div>
  <div class="headertitle">
<div class="title">Startup CAT1C<div class="ingroups"><a class="el" href="group__group__startup__config.html">Startup</a></div></div>  </div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<p>Provides device startup, system configuration, and linker script files. </p>
<p>The system startup provides the followings features:</p><ul>
<li><a class="el" href="group__group__system__config__cm7.html#group_system_config_device_memory_definition_cm7">Device Memory Definition</a></li>
<li><a class="el" href="group__group__system__config__cm7.html#group_system_config_device_initialization_cm7">Device Initialization</a></li>
<li><a class="el" href="group__group__system__config__cm7.html#group_system_config_heap_stack_config_cm7">Heap and Stack Configuration</a></li>
<li><a class="el" href="group__group__system__config__cm7.html#group_system_config_default_handlers_cm7">Default Interrupt Handlers Definition</a></li>
<li><a class="el" href="group__group__system__config__cm7.html#group_system_config_device_vector_table_cm7">Vectors Table Copy from Flash to RAM</a></li>
<li><a class="el" href="group__group__system__config__cm7__functions.html">Cortex-M7 Control</a></li>
</ul>
<h1><a class="anchor" id="group_system_config_configuration_cm7"></a>
Configuration Considerations</h1>
<h2><a class="anchor" id="group_system_config_device_memory_definition_cm7"></a>
Device Memory Definition</h2>
<p>Allocation of different types of memory such as the flash, RAM etc., for the CPU is defined by the linker scripts.</p>
<dl class="section note"><dt>Note</dt><dd>- The linker files provided with the PDL are generic and handle all common use cases. Your project may not use every section defined in the linker files. In that case you may see warnings during the build process. To eliminate build warnings in your project, you can simply comment out or remove the relevant code in the linker file.</dd>
<dd>
- There is a common linker script for both CM7_0 and CM7_1 core. By default it links for CM7_0 core. But if the application is built for CM7_1, then a linker option _CORE_cm7_1 is provided in build system. For example, below piece of code is implemented in the build system. <div class="fragment"><div class="line">ifeq ($(TOOLCHAIN),IAR)</div><div class="line">LDFLAGS += --config_def _CORE_cm7_1_=1</div><div class="line"><span class="keywordflow">else</span> ifeq ($(TOOLCHAIN),GCC_ARM)</div><div class="line">LDFLAGS += -Wl,<span class="stringliteral">&#39;--defsym=_CORE_cm7_1_=1&#39;</span></div><div class="line">endif</div></div><!-- fragment --></dd></dl>
<p><b>ARM GCC</b><br />
 The flash and RAM sections for the CPU are defined in the linker files: 'xx_yy_zz.ld', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example, 'xmc7200d_x8384_cm7.ld', 'xmc7100d_x4160_cm7.ld', 'xmc7200d_x8384_cm0plus.ld' and 'xmc7100d_x4160_cm0plus.ld'. </p><dl class="section note"><dt>Note</dt><dd>If the start of the Cortex-M7_0 or Cortex-M7_1 application image is changed, the value of the <a class="el" href="group__group__system__config__system__macro__cm7.html#gab9058603c83069bd2f36c01b1b77e90c">CY_CORTEX_M7_0_APPL_ADDR</a> or <a class="el" href="group__group__system__config__system__macro__cm7.html#ga25ff69c3a5fcb0e2c89b97a738d986a4">CY_CORTEX_M7_1_APPL_ADDR</a> should also be changed. The <a class="el" href="group__group__system__config__system__macro__cm7.html#gab9058603c83069bd2f36c01b1b77e90c">CY_CORTEX_M7_0_APPL_ADDR</a> or <a class="el" href="group__group__system__config__system__macro__cm7.html#ga25ff69c3a5fcb0e2c89b97a738d986a4">CY_CORTEX_M7_1_APPL_ADDR</a> macro should be used as the parameter for the <a class="el" href="group__group__system__config__cm7__functions.html#gacac741f6dd29eb66dc7e4fb31eef52fe" title="Enables the Cortex-M7 core. ">Cy_SysEnableCM7()</a> function call. By default,<ul>
<li>the COMPONENT_XMC7x_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual-core MCU device (CM0+, CM7_0).</li>
<li>the COMPONENT_XMC7xDUAL_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual CM7-core MCU device (CM0+, CM7_0 and CM7_1).</li>
</ul>
</dd></dl>
<p>Change the flash and RAM sizes by editing the macro values in the linker files for both CPUs:</p><ul>
<li>'xx_yy_cm0plus.ld', where 'xx_yy' is the device group: <div class="fragment"><div class="line">cm0_ram (rxw)  : ORIGIN = _base_SRAM_CM0P, LENGTH = _size_SRAM_CM0P</div><div class="line">cm0_flash (rx) : ORIGIN = _base_CODE_FLASH_CM0P,LENGTH = _size_CODE_FLASH_CM0P</div></div><!-- fragment --></li>
<li>'xx_yy_cm7.ld', where 'xx_yy' is the device group: <div class="fragment"><div class="line">ram (rxw) : ORIGIN = _base_SRAM, LENGTH = _size_SRAM</div><div class="line">flash_cm0p (rx) : ORIGIN = _base_CODE_FLASH_CM0P, LENGTH = _size_CODE_FLASH_CM0P</div><div class="line">flash (rx) : ORIGIN = _base_CODE_FLASH, LENGTH = _size_CODE_FLASH</div></div><!-- fragment --></li>
</ul>
<p>Change the value of the <a class="el" href="group__group__system__config__system__macro__cm7.html#gab9058603c83069bd2f36c01b1b77e90c">CY_CORTEX_M7_0_APPL_ADDR</a> or <a class="el" href="group__group__system__config__system__macro__cm7.html#ga25ff69c3a5fcb0e2c89b97a738d986a4">CY_CORTEX_M7_1_APPL_ADDR</a> macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE value (0x80000, the size of a flash image of the Cortex-M0+ application should be the same value as the flash LENGTH in 'xx_yy_cm0plus.ld') in the 'xx_yy_cm7.ld' file, where 'xx_yy' is the device group.</p>
<ul>
<li>Do this by editing the the <a class="el" href="group__group__system__config__system__macro__cm7.html#gab9058603c83069bd2f36c01b1b77e90c">CY_CORTEX_M7_0_APPL_ADDR</a> or <a class="el" href="group__group__system__config__system__macro__cm7.html#ga25ff69c3a5fcb0e2c89b97a738d986a4">CY_CORTEX_M7_1_APPL_ADDR</a> value in the 'system_xx.h', where 'xx' is the device family:<br />
<div class="fragment"><div class="line"><span class="preprocessor">#define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0</span></div><div class="line"><span class="preprocessor">#define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1</span></div></div><!-- fragment --> 'BASE_CODE_FLASH_CM7_0' and ''BASE_CODE_FLASH_CM7_1' macros are defined in the xmc7xxx_partition.h</li>
</ul>
<p><b>ARM Compiler</b><br />
 The flash and RAM sections for the CPU are defined in the linker files: 'xx_yy_zz.sct', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example 'xmc7200d_x8384_cm7.sct', 'xmc7100d_x4160_cm7.sct', 'xmc7200d_x8384_cm0plus.sct' and 'xmc7100d_x4160_cm0plus.sct'.</p>
<dl class="section note"><dt>Note</dt><dd>If the start of the Cortex-M7_0 or Cortex-M7_1 application image is changed, the value of the <a class="el" href="group__group__system__config__system__macro__cm7.html#gab9058603c83069bd2f36c01b1b77e90c">CY_CORTEX_M7_0_APPL_ADDR</a> or <a class="el" href="group__group__system__config__system__macro__cm7.html#ga25ff69c3a5fcb0e2c89b97a738d986a4">CY_CORTEX_M7_1_APPL_ADDR</a> should also be changed. The <a class="el" href="group__group__system__config__system__macro__cm7.html#gab9058603c83069bd2f36c01b1b77e90c">CY_CORTEX_M7_0_APPL_ADDR</a> or <a class="el" href="group__group__system__config__system__macro__cm7.html#ga25ff69c3a5fcb0e2c89b97a738d986a4">CY_CORTEX_M7_1_APPL_ADDR</a> macro should be used as the parameter for the <a class="el" href="group__group__system__config__cm7__functions.html#gacac741f6dd29eb66dc7e4fb31eef52fe" title="Enables the Cortex-M7 core. ">Cy_SysEnableCM7()</a> function call. By default,<ul>
<li>the COMPONENT_XMC7x_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual-core MCU device (CM0+, CM7_0).</li>
<li>the COMPONENT_XMC7xDUAL_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual CM7-core MCU device (CM0+, CM7_0 and CM7_1).</li>
</ul>
</dd>
<dd>
The linker files provided with the PDL are generic and handle all common use cases. Your project may not use every section defined in the linker files. In that case you may see the warnings during the build process: L6314W (no section matches pattern) and/or L6329W (pattern only matches removed unused sections). In your project, you can suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to the linker. You can also comment out or remove the relevant code in the linker file.</dd></dl>
<p>Change the flash and RAM sizes by editing the macros value in the linker files for both CPUs:</p><ul>
<li>'xx_yy_cm0plus.sct', where 'xx_yy' is the device group: <div class="fragment"><div class="line"><span class="preprocessor">#define SRAM_BASE_ADDRESS               0x28000000</span></div><div class="line"><span class="preprocessor">#define CM0PLUS_SRAM_RESERVE            0x00020000</span></div><div class="line"><span class="preprocessor">#define CODE_FLASH_BASE_ADDRESS         0x10000000</span></div><div class="line"><span class="preprocessor">#define CM0PLUS_CODE_FLASH_RESERVE      0x00080000</span></div></div><!-- fragment --></li>
<li>'xx_yy_cm7.sct', where 'xx_yy' is the device group: <div class="fragment"><div class="line"><span class="preprocessor">#define SRAM_BASE_ADDRESS               0x28000000 //SRAM START</span></div><div class="line"><span class="preprocessor">#define CM7_0_SRAM_RESERVE              0x00060000 //cm7_0 sram size</span></div><div class="line"><span class="preprocessor">#define BASE_SRAM_CM7_0                 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE</span></div><div class="line"><span class="preprocessor">#define SIZE_SRAM_CM7_0                 CM7_0_SRAM_RESERVE</span></div><div class="line"><span class="comment">//In case of dual CM7-core MCU device device</span></div><div class="line"><span class="preprocessor">#define SIZE_SRAM_CM7_1                 SRAM_TOTAL_SIZE - CM0PLUS_SRAM_RESERVE - CM7_0_SRAM_RESERVE</span></div><div class="line"><span class="preprocessor">#define BASE_SRAM_CM7_1                 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE + CM7_0_SRAM_RESERVE</span></div><div class="line"></div><div class="line"><span class="preprocessor">#define CODE_FLASH_BASE_ADDRESS         0x10000000 //FLASH START</span></div><div class="line"><span class="preprocessor">#define CM7_0_CODE_FLASH_RESERVE        0x00200000 //cm7_0 flash size</span></div><div class="line"><span class="preprocessor">#define BASE_CODE_FLASH_CM7_0           CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE</span></div><div class="line"><span class="preprocessor">#define SIZE_CODE_FLASH_CM7_0           CM7_0_CODE_FLASH_RESERVE</span></div><div class="line"><span class="comment">//In case of dual CM7-core MCU device device</span></div><div class="line"><span class="preprocessor">#define BASE_CODE_FLASH_CM7_1           CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE + CM7_0_CODE_FLASH_RESERVE</span></div><div class="line"><span class="preprocessor">#define SIZE_CODE_FLASH_CM7_1           CODE_FLASH_TOTAL_SIZE - CM0PLUS_CODE_FLASH_RESERVE - CM7_0_CODE_FLASH_RESERVE</span></div></div><!-- fragment --></li>
</ul>
<p>Change the value of the <a class="el" href="group__group__system__config__system__macro__cm7.html#gab9058603c83069bd2f36c01b1b77e90c">CY_CORTEX_M7_0_APPL_ADDR</a> or <a class="el" href="group__group__system__config__system__macro__cm7.html#ga25ff69c3a5fcb0e2c89b97a738d986a4">CY_CORTEX_M7_1_APPL_ADDR</a> macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE value (0x80000, the size of a flash image of the Cortex-M0+ application should be the same value as the flash LENGTH in 'xx_yy_cm0plus.sct') in the 'xx_yy_cm7.sct' file, where 'xx_yy' is the device group.</p>
<ul>
<li>Do this by editing the <a class="el" href="group__group__system__config__system__macro__cm7.html#gab9058603c83069bd2f36c01b1b77e90c">CY_CORTEX_M7_0_APPL_ADDR</a> or <a class="el" href="group__group__system__config__system__macro__cm7.html#ga25ff69c3a5fcb0e2c89b97a738d986a4">CY_CORTEX_M7_1_APPL_ADDR</a> value in the 'system_xx.h', where 'xx' is the device family:<br />
<div class="fragment"><div class="line"><span class="preprocessor">#define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0</span></div><div class="line"><span class="preprocessor">#define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1</span></div></div><!-- fragment --> 'BASE_CODE_FLASH_CM7_0' and ''BASE_CODE_FLASH_CM7_1' macros are defined in the xmc7xxx_partition.h</li>
</ul>
<p><b>IAR</b><br />
 The flash and RAM sections for the CPU are defined in the linker files: 'xx_yy_zz.icf', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example, 'xmc7200d_x8384_cm7.icf','xmc7100d_x4160_cm7.icf','xmc7200d_x8384_cm0plus.icf' and 'xmc7100d_x4160_cm0plus.icf'. </p><dl class="section note"><dt>Note</dt><dd>If the start of the Cortex-M7_0 or Cortex-M7_1 application image is changed, the value of the <a class="el" href="group__group__system__config__system__macro__cm7.html#gab9058603c83069bd2f36c01b1b77e90c">CY_CORTEX_M7_0_APPL_ADDR</a> or <a class="el" href="group__group__system__config__system__macro__cm7.html#ga25ff69c3a5fcb0e2c89b97a738d986a4">CY_CORTEX_M7_1_APPL_ADDR</a> should also be changed. The <a class="el" href="group__group__system__config__system__macro__cm7.html#gab9058603c83069bd2f36c01b1b77e90c">CY_CORTEX_M7_0_APPL_ADDR</a> or <a class="el" href="group__group__system__config__system__macro__cm7.html#ga25ff69c3a5fcb0e2c89b97a738d986a4">CY_CORTEX_M7_1_APPL_ADDR</a> macro should be used as the parameter for the <a class="el" href="group__group__system__config__cm7__functions.html#gacac741f6dd29eb66dc7e4fb31eef52fe" title="Enables the Cortex-M7 core. ">Cy_SysEnableCM7()</a> function call. By default,<ul>
<li>the COMPONENT_XMC7x_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual-core MCU device (CM0+, CM7_0).</li>
<li>the COMPONENT_XMC7xDUAL_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual CM7-core MCU device (CM0+, CM7_0 and CM7_1).</li>
</ul>
</dd></dl>
<p>Change the flash and RAM sizes by editing the macros value in the linker files for both CPUs:</p><ul>
<li>'xx_yy_cm0plus.icf', where 'xx_yy' is the device group: <div class="fragment"><div class="line">define symbol sram_base_address                 = 0x28000000;</div><div class="line">define symbol cm0plus_sram_reserve              = 0x00020000; <span class="comment">//cm0 sram size</span></div><div class="line">define symbol code_flash_base_address           = 0x10000000;</div><div class="line">define symbol cm0plus_code_flash_reserve        = 0x00080000; <span class="comment">//cm0 flash size</span></div></div><!-- fragment --></li>
<li>'xx_yy_cm7.icf', where 'xx_yy' is the device group: <div class="fragment"><div class="line">define symbol sram_base_address                 = 0x28000000;</div><div class="line">define symbol cm7_0_sram_reserve                = 0x00060000;</div><div class="line">define symbol _base_SRAM_CM7_0                  = sram_base_address + cm0plus_sram_reserve;</div><div class="line">define symbol _size_SRAM_CM7_0                  = cm7_0_sram_reserve;</div><div class="line"><span class="comment">//In case of dual CM7-core MCU device device</span></div><div class="line">define symbol _base_SRAM_CM7_1                  = sram_base_address + cm0plus_sram_reserve + cm7_0_sram_reserve;</div><div class="line">define symbol _size_SRAM_CM7_1                  = sram_total_size - cm0plus_sram_reserve - cm7_0_sram_reserve;</div><div class="line"></div><div class="line">define symbol code_flash_base_address           = 0x10000000;</div><div class="line">define symbol cm7_0_code_flash_reserve          = 0x00200000;</div><div class="line">define symbol _base_CODE_FLASH_CM7_0            = code_flash_base_address + cm0plus_code_flash_reserve;</div><div class="line">define symbol _size_CODE_FLASH_CM7_0            = cm7_0_code_flash_reserve;</div><div class="line"><span class="comment">//In case of dual CM7-core MCU device device</span></div><div class="line">define symbol _base_CODE_FLASH_CM7_1            = code_flash_base_address + cm0plus_code_flash_reserve + cm7_0_code_flash_reserve;</div><div class="line">define symbol _size_CODE_FLASH_CM7_1            = code_flash_total_size - cm0plus_code_flash_reserve - cm7_0_code_flash_reserve;</div></div><!-- fragment --></li>
</ul>
<p>Change the value of the <a class="el" href="group__group__system__config__system__macro__cm7.html#gab9058603c83069bd2f36c01b1b77e90c">CY_CORTEX_M7_0_APPL_ADDR</a> or <a class="el" href="group__group__system__config__system__macro__cm7.html#ga25ff69c3a5fcb0e2c89b97a738d986a4">CY_CORTEX_M7_1_APPL_ADDR</a> macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE value (0x80000, the size of a flash image of the Cortex-M0+ application should be the same value as the flash LENGTH in 'xx_yy_cm0plus.icf') in the 'xx_yy_cm7.icf' file, where 'xx_yy' is the device group.</p>
<ul>
<li>Do this by editing the <a class="el" href="group__group__system__config__system__macro__cm7.html#gab9058603c83069bd2f36c01b1b77e90c">CY_CORTEX_M7_0_APPL_ADDR</a> or <a class="el" href="group__group__system__config__system__macro__cm7.html#ga25ff69c3a5fcb0e2c89b97a738d986a4">CY_CORTEX_M7_1_APPL_ADDR</a> value in the 'system_xx.h', where 'xx' is the device family:<br />
<div class="fragment"><div class="line"><span class="preprocessor">#define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0</span></div><div class="line"><span class="preprocessor">#define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1</span></div></div><!-- fragment --> 'BASE_CODE_FLASH_CM7_0' and ''BASE_CODE_FLASH_CM7_1' macros are defined in the xmc7xxx_partition.h</li>
</ul>
<h2><a class="anchor" id="group_system_config_device_initialization_cm7"></a>
Device Initialization</h2>
<p>After a power-on-reset (POR), the CM0+ starts boot-ROM directly from ROM and boot-ROM starts CM0+ startup. The CM0+ startup starts CM0+ user application. The CM0+ user application enables CM7 cores and starts CM7 startup. The startup code is the piece of code which is executed after every system reset. It initializes the system components like, memory, FPU, interrupts, clock, etc. and calls application's main() function. The startup code is always build as part of user application. There are two different startup codes for CM0+ and CM7 core.</p>
<p>The CM0+ startup code implements the following functions to run the CM0+ application:</p>
<ol type="1">
<li>In the Reset Handler, it disables global interrupts</li>
<li>Disables the SRAM ECC checking: CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Facelift parts with CM7 core, sets CPUSS-&gt;RAMx_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC has not been initialized yet.</li>
<li>Calls <a class="el" href="group__group__startup__config__system__functions.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="For CAT1A: ">SystemInit()</a> function<ul>
<li>Initializes and enables the SRAM memory for ECC</li>
<li>Copies the vector table from ROM to RAM and updates the VTOR (Vector Table Offset Register)</li>
<li>Sets the CM0+ IRQ0 and IRQ1 handlers from SROM vector table, sets the CM0+ IRQ0 and IRQ1priority, then enables these interrupts: the SROM APIs are executed by CM0+ core in interrupt context using IRQ0 and IRQ1. So, proper interrupt handler addresses and priorities need to be configured for IRQ0 and IRQ1</li>
<li>Unlocks and disable WDT (Watchdog timer)</li>
<li>Calls the <a class="el" href="group__group__startup__config__system__functions.html#gae0c36a9591fe6e9c45ecb21a794f0f0f" title="Gets core clock frequency and updates SystemCoreClock, cy_Hfclk0FreqHz, and cy_PeriClkFreqHz. ">SystemCoreClockUpdate()</a></li>
</ul>
</li>
<li>Executes main() application</li>
</ol>
<p>The CM7 startup code implement the following functions to run the CM7 user application:</p>
<ol type="1">
<li>In the Reset handler, it disables global interrupts</li>
<li>Allows write access to Vector Table Offset Register and ITCM/DTCM configuration register</li>
<li>Enables CM7 core ITCM and DTCM</li>
<li>Enables the FPU if it is used</li>
<li>Copies the vector table from ROM to RAM and updates the VTOR (Vector Table Offset Register)</li>
<li>Enables the CM7 core instruction and data cache</li>
<li>Calls <a class="el" href="group__group__startup__config__system__functions.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="For CAT1A: ">SystemInit()</a> function<ul>
<li>Unlocks and disable WDT (Watchdog timer)</li>
<li>Calls the <a class="el" href="group__group__startup__config__system__functions.html#gae0c36a9591fe6e9c45ecb21a794f0f0f" title="Gets core clock frequency and updates SystemCoreClock, cy_Hfclk0FreqHz, and cy_PeriClkFreqHz. ">SystemCoreClockUpdate()</a></li>
</ul>
</li>
</ol>
<ol type="1">
<li>Executes CM7 main() application</li>
</ol>
<h2><a class="anchor" id="group_system_config_heap_stack_config_cm7"></a>
Heap and Stack Configuration</h2>
<p>By default, the stack size is set to 0x00001000 and the Heap size is allocated dynamically to the whole available free memory up to stack memory. The Stack grows from higher to lower address. The Stack top or start is assigned to end of SRAM address. The Heap grows opposite of Stack. It grows from lower to higher address. The Heap top starts from end of used data section till Stack end.</p>
<h3><a class="anchor" id="group_system_config_heap_stack_config_gcc_cm7"></a>
ARM GCC</h3>
<p><b>Editing source code files</b><br />
 The stack size is defined in the linker script files: 'xx_yy_zz.ld', 'xx_yy_zz.ld', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example, 'xmc7200d_x8384_cm7.ld', 'xmc7100d_x4160_cm7.ld', 'xmc7200d_x8384_cm0plus.ld' and 'xmc7100d_x4160_cm0plus.ld'. Change the stack size by modifying the following line:<br />
</p><div class="fragment"><div class="line">STACK_SIZE = 0x1000; </div></div><!-- fragment --><dl class="section note"><dt>Note</dt><dd>Correct operation of malloc and related functions depends on the working implementation of the 'sbrk' function. Newlib-nano (default C runtime library used by the GNU Arm Embedded toolchain) provides weak 'sbrk' implementation that doesn't check for heap and stack collisions during excessive memory allocations. To ensure the heap always remains within the range defined by __HeapBase and __HeapLimit linker symbols, provide a strong override for the 'sbrk' function: <div class="fragment"><div class="line"><span class="keywordtype">void</span> * _sbrk(uint32_t incr)</div><div class="line">{</div><div class="line">    <span class="keyword">extern</span> uint8_t __HeapBase, __HeapLimit;</div><div class="line">    <span class="keyword">static</span> uint8_t *heapBrk = &amp;__HeapBase;</div><div class="line">    uint8_t *prevBrk = heapBrk;</div><div class="line">    <span class="keywordflow">if</span> (incr &gt; (uint32_t)(&amp;__HeapLimit - heapBrk))</div><div class="line">    {</div><div class="line">        errno = ENOMEM;</div><div class="line">        <span class="keywordflow">return</span> (<span class="keywordtype">void</span> *)-1;</div><div class="line">    }</div><div class="line">    heapBrk += incr;</div><div class="line">    <span class="keywordflow">return</span> prevBrk;</div><div class="line">}</div></div><!-- fragment --> For FreeRTOS-enabled multi-threaded applications, it is sufficient to include clib-support library that provides newlib-compatible implementations of 'sbrk', '__malloc_lock' and '__malloc_unlock': <br />
 <a href="https://github.com/Infineon/clib-support">https://github.com/Infineon/clib-support</a>.</dd></dl>
<h3><a class="anchor" id="group_system_config_heap_stack_config_mdk_cm7"></a>
ARM Compiler</h3>
<p><b>Editing source code files</b><br />
 The stack size is defined in the linker script files: 'xx_yy_zz.sct', 'xx_yy_zz.sct', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example, 'xmc7200d_x8384_cm7.sct', 'xmc7100d_x4160_cm7.sct', 'xmc7200d_x8384_cm0plus.sct' and 'xmc7100d_x4160_cm0plus.sct'. Change the stack size by modifying the following line:<br />
</p><div class="fragment"><div class="line"><span class="preprocessor">#define STACK_SIZE 0x1000 </span></div></div><!-- fragment --><h3><a class="anchor" id="group_system_config_heap_stack_config_iar_cm7"></a>
IAR</h3>
<p><b>Editing source code files</b><br />
 The heap and stack sizes are defined in the linker script files: 'xx_yy_zz.icf', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example, 'xmc7200d_x8384_cm7.icf','xmc7100d_x4160_cm7.icf','xmc7200d_x8384_cm0plus.icf' and 'xmc7100d_x4160_cm0plus.icf'. Change the heap and stack sizes by modifying the following lines:<br />
</p><div class="fragment"><div class="line">define symbol cm7_stack_reserve = 0x00001000; </div></div><!-- fragment --><h2><a class="anchor" id="group_system_config_default_handlers_cm7"></a>
Default Interrupt Handlers Definition</h2>
<p>The default interrupt handler functions are defined as weak functions to a dummy handler in the startup file. The naming convention for the interrupt handler names is &lt;interrupt_name&gt;_IRQHandler. A default interrupt handler can be overwritten in user code by defining the handler function using the same name. For example: </p><div class="fragment"><div class="line"> <span class="keywordtype">void</span> scb_0_interrupt_IRQHandler(<span class="keywordtype">void</span>)</div><div class="line">{</div><div class="line">    ...</div><div class="line">}</div></div><!-- fragment --><h2><a class="anchor" id="group_system_config_device_vector_table_cm7"></a>
Vectors Table Copy from Flash to RAM</h2>
<p>This process uses memory sections defined in the linker script. The startup code actually defines the contents of the vector table and performs the copy.</p>
<h3><a class="anchor" id="group_system_config_device_vector_table_gcc_cm7"></a>
ARM GCC</h3>
<p>The linker script file is 'xx_yy_zz.ld', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example, 'xmc7200d_x8384_cm7.ld', 'xmc7100d_x4160_cm7.ld', 'xmc7200d_x8384_cm0plus.ld' and 'xmc7100d_x4160_cm0plus.ld'. It defines sections and locations in memory.<br />
 Copy interrupt vectors from flash to RAM: <br />
 From:</p><div class="fragment"><div class="line">LONG (<a class="code" href="group__group__sysint__globals.html#ga0b785674909134a8a4045949824befc8">__Vectors</a>) </div></div><!-- fragment --><p> To:</p><div class="fragment"><div class="line">LONG (__ram_vectors_start__) </div></div><!-- fragment --><p> Size:</p><div class="fragment"><div class="line">LONG (__Vectors_End - <a class="code" href="group__group__sysint__globals.html#ga0b785674909134a8a4045949824befc8">__Vectors</a>) </div></div><!-- fragment --><p> The vector table address (and the vector table itself) are defined in the startup files (e.g. startup_cm0plus.S and startup_cm7.c). The code in these files copies the vector table from Flash to RAM.</p>
<h3><a class="anchor" id="group_system_config_device_vector_table_mdk_cm7"></a>
ARM Compiler</h3>
<p>The linker script file is 'xx_yy_zz.sct', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example 'xmc7200d_x8384_cm7.sct', 'xmc7100d_x4160_cm7.sct', 'xmc7200d_x8384_cm0plus.sct' and 'xmc7100d_x4160_cm0plus.sct'. The linker script specifies that the vector table (RESET_RAM) shall be first in the RAM section.<br />
 RESET_RAM represents the vector table. It is defined in the startup files (e.g. startup_cm0plus.S and startup_cm7.c). The code in these files copies the vector table from Flash to RAM.</p>
<h3><a class="anchor" id="group_system_config_device_vector_table_iar_cm7"></a>
IAR</h3>
<p>The linker script file is 'xx_yy_zz.icf', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example, 'xmc7200d_x8384_cm7.icf','xmc7100d_x4160_cm7.icf','xmc7200d_x8384_cm0plus.icf' and ' 'xmc7100d_x4160_cm0plus.icf'.<br />
 The vector table address (and the vector table itself) are defined in the startup files (e.g. startup_cm0plus.S and startup_cm7.c). The code in these files copies the vector table from Flash to RAM.</p>
<h1><a class="anchor" id="group_system_config_changelog_cm7"></a>
Changelog</h1>
<table class="doxtable">
<tr>
<th>Version </th><th>Changes </th><th>Reason for Change  </th></tr>
<tr>
<td>1.0 </td><td>Initial version </td><td></td></tr>
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